1. Field of the Invention
The present invention relates to a semiconductor integrated circuit such as a semiconductor memory device, and more particularly to a clock-synchronous RAM and the like.
2. Description of the Background Art
FIG. 11 is a block diagram showing an overall constitution of an SRAM (SP-SRAM) with one read/write port. As shown in FIG. 11, the SP-SRAM consists of a word line driver 2, an I/O circuit 3, a memory cell array 4, a timing generation circuit 6 and a delay circuit 7.
The memory cell array 4 consists of a plurality of memory cells (not shown) arranged in matrix, and connected to a common word line (not shown) in a unit of row and connected to a common bit line (not shown) in a unit of column. The word line driver 2 receives a signal XDEC serving as a word line drive control signal, comes into an active state when the signal XDEC takes xe2x80x9cHxe2x80x9d (High Level), and selectively activates (opens) the word line on the basis of an externally-received address signal AD.
The I/O circuit 3 includes an input/output buffer, a sense amplifier, a write driver and a precharge circuit (all of which are not shown) therein. The sense amplifier comes into an active state when a sense amplifier activation signal SE takes xe2x80x9cHxe2x80x9d, and when in the active state, it detects and amplifies read data given from a selected memory cell in the memory cell array and externally outputs the data as output data. The write driver comes into an active state when a driver control signal WE takes xe2x80x9cHxe2x80x9d, when in the active state, it outputs write data based on externally-received input data to the selected memory cell through a pair of bit lines. The precharge circuit comes into an active state when a precharge control signal PC takes xe2x80x9cHxe2x80x9d, and when in the active state, it precharges the pair of bit lines in the memory cell array 4 to a predetermined potential.
The timing generation circuit 6 receives a clock signal CLOCK, a signal WEC and a signal READY and outputs the signal XDEC, the: signal SE, the signal WE, the signal PC and a signal DUM_XDEC all of which serve as control signals.
The delay circuit 7 outputs the signal READY of xe2x80x9cLxe2x80x9d (Low Level) after a delay time xcex94T2 passes from the point of time when the signal DUM_XDEC changes from xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d and outputs the signal READY of xe2x80x9cHxe2x80x9d immediately after the signal DUM_XDEC changes from xe2x80x9cLxe2x80x9d to xe2x80x9cHxe2x80x9d. The delay time xcex94T2 is so set as to satisfy both a time required to activate the word line in the memory cell array 4 and detect and amplify the read data by the sense amplifier in a read mode and a time required to store the write data given from the write driver into the selected memory cell in a write mode.
FIG. 12 is a circuit diagram showing an internal configuration of the timing generation circuit 6 shown in FIG. 11. As shown in FIG. 12, inverters G51 and G52 are connected in series, and an input of the inverter G51 receives the clock signal CLOCK. One input of a NAND gate G54 receives an output from the inverter G52 and the other input receives the signal READY. An input of an inverter G56 receives an output from the NAND gate G54 and an input of an inverter G57 receives an output from the inverter G56.
On the other hand, an input of an inverter G55 receives the signal READY. One input of a NAND gate G58 receives an output from the inverter G55 and the other input receives the output from the inverter G52. An input of an inverter G59 receives an output from the NAND gate G58. One input of a NOR gate G60 receives the signal XDEC and the other input receives an output from the inverter G59.
Further, an input of an inverter G53 receives the signal WEC. One input of a NOR gate G61 receives the signal WEC and the other input receives the output from the NAND gate G54. One input of a NOR gate G62 receives an output from the inverter G53 and the other input receives the output from the NAND gate G54. Inverters G63 and G64 are connected in series, and an input of the inverter G63 receives an output from the NOR gate G61. Inverters G65 and G66 are connected in series, and an input of the inverter G65 receives an output from the NOR gate G62.
An output of the inverter G57 is outputted as the precharge control signal PC. An output of the inverter G56 is outputted as the signal XDEC. An output of the NOR gate G60 is outputted as the signal DUM_XDEC. An output of the inverter G64 is outputted as the sense amplifier activation signal SE. An output of the inverter G66 is outputted as the driver control signal WE.
FIG. 13 is a timing chart showing a generating operation of the timing generation circuit 6 shown in FIG. 12. Referring to FIG. 13, the operation of the timing generation circuit 6 will be discussed below.
First, in an initial state, the signal XDEC is set to xe2x80x9cLxe2x80x9d, the signal READY is set to xe2x80x9cHxe2x80x9d and the signal DUM_XDEC is set to xe2x80x9cHxe2x80x9d. Further, it is assumed here that the timing generation circuit 6 is in a read mode with the write control signal WEC of xe2x80x9cLxe2x80x9d. In the read mode, the driver control signal WE is fixed to xe2x80x9cLxe2x80x9d.
In the initial state, when the clock signal CLOCK rises to xe2x80x9cHxe2x80x9d, the signal XDEC changes to xe2x80x9cHxe2x80x9d (change CH11) with rise of the clock signal CLOCK to xe2x80x9cHxe2x80x9d as a trigger since the signal READY takes xe2x80x9cHxe2x80x9d.
At the same time as the change CH11, the precharge control signal PC and the signal DUM_XDEC fall to xe2x80x9cLxe2x80x9d and the sense amplifier activation signal SE rises to xe2x80x9cHxe2x80x9d.
When the signal XDEC takes xe2x80x9cHxe2x80x9d, the word line driver 2 comes into an active state and selectively drives the word line (into the active state) on the basis of the externally-received address signal AD.
At the same time, the precharge circuit comes into an inactive state with the precharge control signal PC of xe2x80x9cLxe2x80x9d, and the sense amplifier comes into an active state with the sense amplifier activation signal SE of xe2x80x9cHxe2x80x9d to externally output the read data from the selected memory cell as the output data which is detected and amplified, starting a read operation.
Then, after the delay time xcex94T2 passes from the rise of the signal XDEC (the fall of the signal DUM_XDEC), the signal READY falls to xe2x80x9cLxe2x80x9d (change CH12).
The signal XDEC falls to xe2x80x9cLxe2x80x9d (change CH13) with the fall of the signal READY to xe2x80x9cLxe2x80x9d. At the same time, the precharge control signal PC rises to xe2x80x9cHxe2x80x9d and the sense amplifier activation signal SE falls to xe2x80x9cLxe2x80x9d.
With the signal XDEC of xe2x80x9cLxe2x80x9d, the word line driver 2 comes into an inactive state to stop driving all the word lines, and with the sense amplifier activation signal SE of xe2x80x9cLxe2x80x9d, the sense amplifier comes into an inactive state, terminating the read operation. On the other hand, with the precharge control signal PC of xe2x80x9cHxe2x80x9d, a precharge operation on the pair of bit lines restarts.
Further, since the signal READY takes xe2x80x9cLxe2x80x9d, the signal DUM_XDEC sustains xe2x80x9cLxe2x80x9d even when the signal XDEC falls to xe2x80x9cLxe2x80x9d.
After that, when the clock signal CLOCK falls to xe2x80x9cLxe2x80x9d, the signal DUM_XDEC rises to xe2x80x9cHxe2x80x9d (change CH14) with fall of the clock signal CLOCK to xe2x80x9cLxe2x80x9d as a trigger.
Further, after the signal DUM_XDEC rises to xe2x80x9cHxe2x80x9d, the signal READY rises to xe2x80x9cHxe2x80x9d (change CH15) immediately. As a result, the signal XDEC comes into xe2x80x9cLxe2x80x9d and the signal READY and the signal DUM_XDEC come into xe2x80x9cHxe2x80x9d, returning to the initial state. After that, in synchronization with the clock signals CLOCK, the above operation is repeated.
Thus, the timing generation circuit 6 generates the signal XDEC, the precharge control signal PC and the sense amplifier activation signal SE all of which serve as the operation control signals, performing a timing control of the read operation.
Further, with the signal WEC of xe2x80x9cHxe2x80x9d, the timing generation circuit 6 comes into a write mode. Specifically, the timing generation circuit 6 generates the sense amplifier activation signal SE which is fixed to xe2x80x9cLxe2x80x9d, the driver control signal WE which changes like the sense amplifier activation signal SE in the read mode, and the signal XDEC and the precharge control signal Pc which change like those in the read mode, performing a timing control of the write operation.
Since the timing generation circuit 6 in the background art has a circuit configuration in which the logics and the clocks are combined as discussed above, the timing of generating the control signals (XDEC, WE, SE and PC) generated in the timing generation circuit 6 is constrained by the time length of xe2x80x9cHxe2x80x9d (xe2x80x9cLxe2x80x9d) period of the clock signal CLOCK and a high-speed operation of RAM is disadvantageously impeded.
For example, during a period while the signal XDEC takes xe2x80x9cHxe2x80x9d and the signal READY takes xe2x80x9cHxe2x80x9d after the signal change CH11 of FIG. 13 and the word line is driven to perform the read operation (write operation), when the clock signal CLOCK falls to xe2x80x9cLxe2x80x9d, the signal XDEC falls to xe2x80x9cLxe2x80x9d and accordingly the driving operation of the word line is forcedly terminated, to fail the read operation (write operation). Therefore, at least until the signal XDEC falls with the fall of the signal READY as a trigger, the clock signal CLOCK needs to sustain xe2x80x9cHxe2x80x9d.
The present invention is directed to a semiconductor integrated circuit. According to a first aspect of the present invention, the semiconductor integrated circuit comprises: a control unit for generating an operation control signal in synchronization with a clock signal; an operation unit for operating on the basis of the operation control signal, and in the semiconductor integrated circuit of the first aspect, the control unit outputs the operation control signal which is timing-controlled only by a single predetermined kind of signal shift of the clock signal.
According to a second aspect of the present invention, in the semiconductor integrated circuit of the first aspect, the control unit comprises a pulse generation circuit receiving the clock signal, for generating a pulse signal taking a first level or a second level, the pulse signal coming into the first level for a predetermined period from the single predetermined kind of signal shift of the clock signal; a latch circuit receiving the pulse signal, for outputting a latch signal having a signal value based on the first level in response to the pulse signal of the first level, and after that coming into a data holding state for a predetermined period to hold the signal value of the latch signal regardless of the level of the pulse signal; and a control signal generation circuit for generating the operation control signal on the basis of the latch signal.
According to a third aspect of the present invention, in the semiconductor integrated circuit of the second aspect, the control unit further comprises an operation control signal high-speed setting circuit for making the control signal generation circuit generate the operation control signal which is generated by the control signal generation circuit in response to the latch signal in advance before the control signal generation circuit is driven by the latch signal, when the pulse signal takes the first level.
According to a fourth aspect of the present invention, in the semiconductor integrated circuit of the second aspect, the control unit further comprises an auxiliary signal outputting circuit for outputting an auxiliary signal on the basis of the operation control signal, and the latch circuit releases the data holding state when the auxiliary signal takes a predetermined signal value.
According to a fifth aspect of the present invention, in the semiconductor integrated circuit of the fourth aspect, the control unit further comprises an operation control signal high-speed setting circuit for making the control signal generation circuit generate the operation control signal which is generated by the control signal generation circuit in response to the latch signal in advance before the control signal generation circuit is driven by the latch signal, when the auxiliary signal takes the predetermined signal value.
According to a sixth aspect of the present invention, in the semiconductor integrated circuit of the fourth or fifth aspect, the auxiliary signal outputting circuit includes a delay circuit receiving the operation control signal, for outputting the auxiliary signal of the predetermined signal value on the basis of a delayed signal of the operation control signal.
Preferably, the operation unit includes a semiconductor memory unit constituted of a memory cell array having a plurality of memory cells arranged in matrix.
Preferably, the operation control signal includes an operation control signal for selecting the memory cells of the memory cell array.
Preferably, the operation control signal high-speed setting circuit includes a first transistor having one electrode receiving a fixed potential, the other electrode connected to a node which determines a signal value of the operation control signal, and a control electrode receiving a pulse-related signal which takes a signal value corresponding to a signal value of the pulse signal, and the first transistor comes into an on state when the pulse-related signal takes a signal value set correspondingly to the first level of the pulse signal.
Preferably, the latch circuit has a first NAND gate and a second NAND gate, the first NAND gate has one input receiving the pulse signal and the other input receiving an output from the second NAND gate and outputs the latch signal, the second NAND gate has one input receiving the latch signal and the other input receiving the auxiliary signal, the first level includes xe2x80x9cLxe2x80x9d level, and the predetermined level includes xe2x80x9cLxe2x80x9d level.
Preferably, the latch circuit has a first NOR gate and a second NOR gate, the first NOR gate has one input receiving the pulse signal and the other input receiving an output from the second NOR gate and outputs the latch signal, the second NOR gate has one input receiving the latch signal and the other input receiving an inverted signal of the auxiliary signal, the first level includes xe2x80x9cHxe2x80x9d level, and the predetermined level includes xe2x80x9cLxe2x80x9d level.
Preferably, the operation control signal high-speed setting circuit includes a second transistor having one electrode receiving a fixed potential, the other electrode connected to a node which determines a signal value of the operation control signal, and a control electrode receiving an auxiliary-related signal which takes a signal value corresponding to a signal value of the auxiliary signal, and the second transistor comes into an on state when the auxiliary-related signal takes a signal value set correspondingly to the predetermined level of the auxiliary signal.
In the semiconductor integrated circuit of the first aspect of the present invention, since the control unit can output the operation control signal which is unconstrained by a signal level sustain period of the clock signal by outputting the operation control signal which is timing-controlled only by the single predetermined kind of signal shift of the clock signal, it is possible to achieve a high-speed operation of the operation unit.
In the semiconductor integrated circuit of the second aspect of the present invention, the latch circuit of the control unit receives the pulse signal which comes into he first level for a predetermined period from the single predetermined kind of signal shift of the clock signal, with the pulse signal of the first level unconditionally taken, outputs the latch signal having the signal value based on the first level, and then comes into the data holding state for a predetermined period to hold the signal value of the latch signal regardless of a signal value of the pulse signal.
Therefore, it is possible to generate the operation control signal on the basis of the signal value of the latch signal at a timing depending only on the single predetermined kind of signal shift of the clock signal.
In the semiconductor integrated circuit of the third aspect of the present invention, since the operation control signal high-speed setting circuit makes the control signal generation circuit generate the operation control signal which is generated by the control signal generation circuit in response to the latch signal in advance before the control signal generation circuit is driven by the latch signal when the pulse signal takes the first level, it is possible to set the signal value of the operation control signal at high speed with the single predetermined kind of signal shift (change of the pulse signal from the second level to the first level) of the clock signal as a trigger.
In the semiconductor integrated circuit of the fourth aspect of the present invention, since the latch circuit releases the data holding state when the auxiliary signal takes the predetermined signal value, it is possible to control the timing of terminating the output of the latch signal having the signal value based on the first level with the auxiliary signal.
In the semiconductor integrated circuit of the fifth aspect of the present invention, since the operation control signal high-speed setting circuit makes the control signal generation circuit generate the operation control signal which is generated by the control signal generation circuit in response to the latch signal in advance before the control signal generation circuit is driven by the latch signal when the auxiliary signal takes the predetermined signal value, it is possible to set the signal value of the operation control signal at high speed with a signal change of the auxiliary signal to a predetermined signal value as a trigger.
In the semiconductor integrated circuit of the sixth aspect of the present invention, since the delay circuit outputs the auxiliary signal having the predetermined signal value on the basis of the delayed signal of the operation control signal, it is possible to set the timing of outputting the auxiliary signal of predetermined level, depending on a signal change of the operation control signal.
An object of the present invention is to provide a semiconductor integrated circuit having a control unit which generates an operation control signal in synchronization with a clock signal for an operation unit of a RAM such as a memory cell array, a word line driver and an I/O circuit and is unconstrained by the time length of xe2x80x9cHxe2x80x9d (xe2x80x9cLxe2x80x9d) period of the clock signal.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.